How a CPU Microprocessor Is Made

This is a quick tutorial to help you understand how microprocessors and other integrated circuits are made, or 'fabbed.' Starting from a chunk of silicon and resulting in a device with millions and millions of transistors that now run almost everything in your life.

Making the Wafer

CPUs are made mostly of an element called silicon. Silicon is rather common in earths crust and is a semiconductor. This means that depending on what materials you add to it, it can conduct when a voltage is applied to it. It is the 'switch that makes a CPU work. Modern CPUs literally contain millions transistors.

Raw silicon

The first stage in making a CPU is to make the wafers that they are built on. This process begins with the melting of polysilicon, together with minute amounts of electrically active elements such as arsenic, boron, phosphorous or antimony in a quartz crucible (a container that won't melt at high temperatures).


Silicon is a simple FCC Lattice (Face Centered Cubic)

Once the melt has reached the desired temperature, we lower a silicon seed crystal, or "seed" into the melt. The melt is slowly cooled to the required temperature, and crystal growth begins around the seed. As the growth continues, the seed is slowly extracted or "pulled" from the melt. As the the ingot is pulled it is slowly rotated. This is done to help normalize any temperature variations in the melt. The temperature of the melt and the speed of extraction govern the diameter of the ingot, and the concentration of an electrically active element in the melt governs the electrical properties of the silicon wafers to be made from the ingot. This is a complex, proprietary process requiring many control features on the crystal-growing equipment. The crystals naturally tend to a circular shape due to the crystal structure itself, and the surface tension on the liquid.

6" ingot is drawn out of the melt. This process can take several hours.

This results in a large ingot that looks like this:

To be useful the ingot must be very pure. The ends and edges are the areas of highest impurities (this is due to annealing) so the ends are cut off and the edges are ground down so the ingot is the proper diameter.

Next the wafers are cut from the ingot. They are usually cut 1-2mm thick with a fast wire saw. The edges of these wafers are then rounded to prevent chipping and edge cracks. The wafers are then ground and polished both chemically and mechanically to produce a very flat, mirror like surface.


Wafers may then be heated to help remove any defects. (annealing)

The wafers are then inspected with a laser to find any surface defects.

A single crystal layer (epilayer) may then be added to the surface of the wafer.
The wafer is now ready for etching.

Etching

1. Oxide	A layer of oxide is implanted on the wafer. This is most often done by exposing the wafer to steam at very high temperatures
2. Photoresist	A layer of organic photoresist is applied. This is like film in a camera
3. Masking	A mask is applied and UV light is shown through the gaps. UV light is now used because of its shorter wavelength. A shorter wavelength means that it can pass through a smaller mask. The UV light hardens (fixes) the photoresist.
4. Cleaning	The unhardened mask is removed with an organic solvent
5. Etching	Hydroflouric (HF) acid is used to etch away the Silicon Oxide. Since HF is inorganic it does not attack the photoresist.
6. Cleaning	The remaining photoresist is washed away. The wafer is now ready for doping with another type of silicon. Or for adding contacts.

Making the tranisistor

(A)	A p-type wafer (silicon doped with Boron) has a epilayer of n-type (silicon doped with Phosphorous or Arsenic)
(B)	A mask is used to implant Silicon Dioxide, for the insulator
(C)	Acceptor atoms (Boron) are diffused into the window in the Silicon Dioxide
(D)	Using another mask additional Silicon Dioxide is grown. and donor atoms (elements like Arsenic with excess electrons) are implanted.
(E)	Another mask is used to grow additional Silicon Dioxide. ANother mask is then used to implant evaporated Aluminum or Copper for the contacts. This is a Bipolar Junction Transistor (BJT).

MOS Tranistor

These transistors are what are used in microprocessors and memory. They take less power then BJTs but are made in the exact same way.

This work is all done in 'clean rooms' as even the smallest particle of dust can wreck a whole chip!!
The workers wear 'bunny suits' to keep dust and skin particales from getting into the air.


These days much of the process is automated so the technicians have to monitor alot of sophisticated machines.


A fab requires large amounts of infrastructure to deal with all the chemicals, high temperatures, and pressures.

Intel fab - external plumbing

Many many chips can fit on one 300mm wafer.

Once the wafer full of chips is made each chip is tested while stll on the wafer. If a bad one is found it is marked so that it is not used. Most bad chips tend to be areound the edge of the wafer. The best chips are in the center and are sometimes selected for extended temperature testing for military or industrial use.

The wafer is then cut up into its individual chips. These chips are what gets 'bonded' to the packge that is in your computer.
Typically the bonding is done in countries where labout costs are low. The facilities to do so can be quite large.

This is an assembly facility in Costa Rica.
Thie final product may take 3 months to complete
A CPU with 25+ million transistors is impressive by any standards.

New Technologies

Silicon on Insulator (SOI)	Silicon-on-Insulator (SOI) Silicon-on-Insulator (SOI) is a manufacturing technology where an insulating layer is created in a silicon wafer, isolating the top layer of silicon where the active transistors will be manufactured from the rest of the bulk silicon wafer. The buried oxide layer acts as a barrier that reduces electrical leakage from the transistors, resulting in semiconductor devices that are faster and more power efficient. These benefits make SOI a valuable technology for chipmakers producing IC's for high performance applications such as servers and workstations, portable and desktop computers, wireless communication devices, integrated optical components and automotive electronics. SOI is by no means new. It was used on the RCA COSMAC 1802 in 1976. This chip used Sapphire (Al2O3) for the insulator and ran at a then blazing 6.4MHz. SOI or SOS technology has the added benefit of making the chip less prone to radiation errors. This is why the RCA COSMAC was used on the Pioneer, Voyager, and Galileo space probes.
Immersion Lithography	Immersion lithography is a projection enhancement methodology that places a liquid between the lens and the wafer. The additional refraction of the light passing through the liquid works to enhance the resolution achievable by the projected light. IBM thinks that the immersion litho process could enable 193 nm tools to produce silicon circuit features as small as 45 nm, and maybe even smaller. And to think there was a small industry gasp just over a year ago when Intel announced it could stretch 193 nm tools to produce 65 nm transistor-based chips.
Copper	Copper is a technology that is now generally in wide use. Instead of using Aluminum interconnects and contact padsm copper is now used. It has a lower resistance allowing for higher speeds and lower power consumption.
Low-K Dielectrics	Low-k dielectrics are used to form insulation between interconnects in integrated circuits. The lower the k-value, the better the insulator. The ideal insulator is air, which has a k-value of one. However, it currently isn't feasible to make complex integrated circuits with only air between the wires, a technique known as "silicon-on-nothing (SON). As a result, researchers are examining dielectric materials that are as porous as possible (to maximize the amount of air), yet durable enough to withstand the rigors of the chipmaking process. Novellus has introduced a material with a k-value of 1.7, which is considerably better than the dielectric materials currently employed. Most dielectrics are inserted onto chips by either spin-on processes or by Chemical Vapor Deposition (CVD). Novellus uses a CVD approach for the dielectric material, which the company claims is hard enough to withstand the chipmaking process. The better the dielectric, the less space between wires. This means smaller, faster parts.
Strained Germanium	Germanium has been used in smaller doses by several companies, including IBM, in an existing manufacturing technique called strained silicon. In this technique, a mixture of germanium and silicon is placed next to a layer of pure silicon, which causes the silicon atoms to stretch in order to align themselves with the silicon germanium atoms. This opens a wider path that allows more electrons to flow through the circuit. Researchers have long known that germanium is a better conductor of electricity than silicon, but they had not figured out how to build higher concentrations of germanium into chips using conventional techniques.. IBM has accomplished this, and has also figured out how to strain the germanium layer in order to further improve performance. Germanium, which is a by-product of zinc ore processing, is a hard element with the same crystal structure as a diamond. It is a semiconductor with electrical properties between those produced by a metal and an insulator. Its use as a transistor was key in the advancement of solid-state electronics.
EUV - Extreme UltraViolet	EUV is simply shorter wavelength (13nm) V process lithography. This allows for using masks to make smaller features. It is leading to X-ray lithography which is even shorter wavelength.
Separation-by-IMplantation-of-OXygen (SIMOX)	Separation by Implantation of Oxygen (SIMOX) is a radically new fabrication technique. SIMOX works by creating a perfectly smooth .15-micron layer of silicon oxide SOI film. This new SOI film features virtually no imperfections or impurities while retaining high yield rates. The SIMOX process involves direct injection of purified oxygen into a silicon wafer at extremely high temperatures. Under the high temperature, oxygen bonds with the silicon, forming the thin layers of silicon oxide film. This relatively perfect silicon oxide allows direct bonding to the pure crystalline silicon substrate.